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HASH      36953a4cb607
DATE      2025-05-14
SUBJECT   hardware: cpu options
FILES     1 CHANGED
HASH      36953a4cb607
DATE      2025-05-14
SUBJECT   hardware: cpu options
FILES     1 CHANGED
 

diff --git a/modules/nixos/hardware/cpu/options.nix b/modules/nixos/hardware/cpu/o
ptions.nix
index 618dc79..ce1356f 100644
--- a/modules/nixos/hardware/cpu/options.nix
+++ b/modules/nixos/hardware/cpu/options.nix
@@ -37,92 +37,101 @@ in {
         default = null;
         description = "CPU stepping from CPUID";
       };
+      name = mkOption {
+        type = nullOr str;
+        default = null;
+        description = "CPU Model Name";
+        example = "Intel(R) Core(TM) i3-10100 CPU @ 3.60GHz";
+      };
+      microArchitecture = mkOption {
+        type = str;
+        default = lookupMicroArch cfg;
+        description = "CPU microarchitecture (e.g, skylake, zen4)";
+        readOnly = true;
+      };
     };
 
-    name = mkOption {
-      type = nullOr str;
-      default = null;
-      description = "CPU Model Name";
-      example = "Intel(R) Core(TM) i3-10100 CPU @ 3.60GHz";
-    };
-
-    tdp = mkOption {
-      type = nullOr int;
-      default = null;
-      description = ''
-        Thermal Design Power in watts.
-        Must be manually specified based on CPU model.
-        Refer to manufacturer specifications:
-        - Intel: https://ark.intel.com
-        - AMD: https://www.amd.com/en/products/specifications.html
-      '';
-      example = 65;
-    };
-
-    baseClock = mkOption {
-      type = nullOr float;
-      default = null;
-      description = "Base clock frequency in GHz";
-      example = 3.8;
-    };
-
-    boostClock = mkOption {
-      type = nullOr float;
-      default = null;
-      description = "Boost clock frequency in GHz";
-      example = 4.7;
-    };
-
-    cores = mkOption {
-      type = int;
-      description = "Number of Physical CPU cores the system has";
-    };
-
-    threadsPerCore = mkOption {
-      type = int;
-      default = 1;
-      descrpition = "Number of threads per physical core (hyperthreading)";
-    };
-
-    totalThreads = mkOption {
-      type = int;
-      default = cfg.cpu.cores * cfg.cpu.threadsPerCore;
-      description = "Number of cpu threads the cpu has";
-      readOnly = true;
-    };
-
-    cache = {
-      l1i = mkOption {
+    spec = {
+      sockets = mkOption {
         type = nullOr int;
+        default = 1;
+        description = "Number of CPU sockets";
+      };
+      baseClock = mkOption {
+        type = nullOr float;
         default = null;
-        description = "Size of L1 instruction cache in KiB";
-        example = 192;
+        description = "Base clock frequency in GHz";
+        example = 3.8;
       };
-      l1d = mkOption {
-        type = nullOr int;
+
+      boostClock = mkOption {
+        type = nullOr float;
         default = null;
-        description = "Size of L1 data cache in KiB";
-        example = 192;
+        description = "Boost clock frequency in GHz";
+        example = 4.7;
       };
-      l2 = mkOption {
+
+      coresPerSocket = mkOption {
         type = nullOr int;
         default = null;
-        description = "Size of L2 cache in MiB";
-        example = 6;
+        description = "Number of Physical CPU core per socket";
+      };
+
+      threadsPerCore = mkOption {
+        type = int;
+        default = 1;
+        description = "Number of threads per physical core (hyperthreading)";
+      };
+
+      totalThreads = mkOption {
+        type = int;
+        default =
+          if cfg.spec.sockets == null || cfg.spec.coresPerSocket == null
+          then null
+          else (cfg.cpu.spec.coresPerSocket * cfg.cpu.spec.sockets) * cfg.cpu.spe
c.threadsPerCore;
+        description = "Number of cpu threads the cpu has";
+        readOnly = true;
       };
-      l3 = mkOption {
+
+      tdp = mkOption {
         type = nullOr int;
         default = null;
-        description = "Size of L3 cache in MiB";
-        example = 32;
+        description = ''
+          Thermal Design Power in watts.
+          Must be manually specified based on CPU model.
+          Refer to manufacturer specifications:
+          - Intel: https://ark.intel.com
+          - AMD: https://www.amd.com/en/products/specifications.html
+        '';
+        example = 65;
       };
-    };
 
-    microArchitecture = mkOption {
-      type = str;
-      default = lookupMicroArch cfg;
-      description = "CPU microarchitecture (e.g, skylake, zen4)";
-      readOnly = true;
+      cache = {
+        l1i = mkOption {
+          type = nullOr int;
+          default = null;
+          description = "Size of L1 instruction cache in Bytes";
+          example = 192;
+        };
+        l1d = mkOption {
+          type = nullOr int;
+          default = null;
+          description = "Size of L1 data cache in Bytes";
+          example = 192;
+        };
+        l2 = mkOption {
+          type = nullOr int;
+          default = null;
+          description = "Size of L2 cache in Bytes";
+          example = 6;
+        };
+        l3 = mkOption {
+          type = nullOr int;
+          default = null;
+          description = "Size of L3 cache in Bytes";
+          example = 32;
+        };
+      };
     };
 
     amd.pstate.enable = mkEnableOption "";


diff --git a/modules/nixos/hardware/cpu/opti
ons.nix b/modules/nixos/hardware/cpu/options
.nix
index 618dc79..ce1356f 100644
--- a/modules/nixos/hardware/cpu/options.nix
+++ b/modules/nixos/hardware/cpu/options.nix
@@ -37,92 +37,101 @@ in {
         default = null;
         description = "CPU stepping from CP
UID";
       };
+      name = mkOption {
+        type = nullOr str;
+        default = null;
+        description = "CPU Model Name";
+        example = "Intel(R) Core(TM) i3-101
00 CPU @ 3.60GHz";
+      };
+      microArchitecture = mkOption {
+        type = str;
+        default = lookupMicroArch cfg;
+        description = "CPU microarchitectur
e (e.g, skylake, zen4)";
+        readOnly = true;
+      };
     };
 
-    name = mkOption {
-      type = nullOr str;
-      default = null;
-      description = "CPU Model Name";
-      example = "Intel(R) Core(TM) i3-10100
 CPU @ 3.60GHz";
-    };
-
-    tdp = mkOption {
-      type = nullOr int;
-      default = null;
-      description = ''
-        Thermal Design Power in watts.
-        Must be manually specified based on
 CPU model.
-        Refer to manufacturer specification
s:
-        - Intel: https://ark.intel.com
-        - AMD: https://www.amd.com/en/produ
cts/specifications.html
-      '';
-      example = 65;
-    };
-
-    baseClock = mkOption {
-      type = nullOr float;
-      default = null;
-      description = "Base clock frequency i
n GHz";
-      example = 3.8;
-    };
-
-    boostClock = mkOption {
-      type = nullOr float;
-      default = null;
-      description = "Boost clock frequency 
in GHz";
-      example = 4.7;
-    };
-
-    cores = mkOption {
-      type = int;
-      description = "Number of Physical CPU
 cores the system has";
-    };
-
-    threadsPerCore = mkOption {
-      type = int;
-      default = 1;
-      descrpition = "Number of threads per 
physical core (hyperthreading)";
-    };
-
-    totalThreads = mkOption {
-      type = int;
-      default = cfg.cpu.cores * cfg.cpu.thr
eadsPerCore;
-      description = "Number of cpu threads 
the cpu has";
-      readOnly = true;
-    };
-
-    cache = {
-      l1i = mkOption {
+    spec = {
+      sockets = mkOption {
         type = nullOr int;
+        default = 1;
+        description = "Number of CPU socket
s";
+      };
+      baseClock = mkOption {
+        type = nullOr float;
         default = null;
-        description = "Size of L1 instructi
on cache in KiB";
-        example = 192;
+        description = "Base clock frequency
 in GHz";
+        example = 3.8;
       };
-      l1d = mkOption {
-        type = nullOr int;
+
+      boostClock = mkOption {
+        type = nullOr float;
         default = null;
-        description = "Size of L1 data cach
e in KiB";
-        example = 192;
+        description = "Boost clock frequenc
y in GHz";
+        example = 4.7;
       };
-      l2 = mkOption {
+
+      coresPerSocket = mkOption {
         type = nullOr int;
         default = null;
-        description = "Size of L2 cache in 
MiB";
-        example = 6;
+        description = "Number of Physical C
PU core per socket";
+      };
+
+      threadsPerCore = mkOption {
+        type = int;
+        default = 1;
+        description = "Number of threads pe
r physical core (hyperthreading)";
+      };
+
+      totalThreads = mkOption {
+        type = int;
+        default =
+          if cfg.spec.sockets == null || cf
g.spec.coresPerSocket == null
+          then null
+          else (cfg.cpu.spec.coresPerSocket
 * cfg.cpu.spec.sockets) * cfg.cpu.spec.thre
adsPerCore;
+        description = "Number of cpu thread
s the cpu has";
+        readOnly = true;
       };
-      l3 = mkOption {
+
+      tdp = mkOption {
         type = nullOr int;
         default = null;
-        description = "Size of L3 cache in 
MiB";
-        example = 32;
+        description = ''
+          Thermal Design Power in watts.
+          Must be manually specified based 
on CPU model.
+          Refer to manufacturer specificati
ons:
+          - Intel: https://ark.intel.com
+          - AMD: https://www.amd.com/en/pro
ducts/specifications.html
+        '';
+        example = 65;
       };
-    };
 
-    microArchitecture = mkOption {
-      type = str;
-      default = lookupMicroArch cfg;
-      description = "CPU microarchitecture 
(e.g, skylake, zen4)";
-      readOnly = true;
+      cache = {
+        l1i = mkOption {
+          type = nullOr int;
+          default = null;
+          description = "Size of L1 instruc
tion cache in Bytes";
+          example = 192;
+        };
+        l1d = mkOption {
+          type = nullOr int;
+          default = null;
+          description = "Size of L1 data ca
che in Bytes";
+          example = 192;
+        };
+        l2 = mkOption {
+          type = nullOr int;
+          default = null;
+          description = "Size of L2 cache i
n Bytes";
+          example = 6;
+        };
+        l3 = mkOption {
+          type = nullOr int;
+          default = null;
+          description = "Size of L3 cache i
n Bytes";
+          example = 32;
+        };
+      };
     };
 
     amd.pstate.enable = mkEnableOption "";

 
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